[stella] PF register write timing

[bob.montgomery at thomson.com]

Hi Rob,

>Has anyone ever done a comprehensive study to determine what the  
>absolute last cycle you can write to a PFx register is and not see  
>any corruption.    For example with the first instance of PF1 on the  
>left side, does the write to PF1 need to end on cycle 23, 24, 25, or  
>26 for all 8 PF pixels to render correctly?

I know that you can write to PF1 (first instance) as late as cycle 27
with no corruption, but no later.

I use this code to write an asym playfield in my Metroid WIP, which 
only uses PF1 and PF2 with an asymmetrical, reflected playfield:

	lda PFL,X
	sta PF1			;+7	27
	lda PFCL,X
	sta PF2			;+7	34
	lda PFR,X
	sta PF1			;+7	41
	lda PFCR,X
	sta PF2			;+28	48

I've done some testing here and there and I think you basically need
at least 1 full machine cycle between the write to the PF register and
when
TIA starts drawing that register to the screen.

I.e., TIA starts drawing each register at these times (non reflected):
PF0: 22.67 cycles, needs to be written by cycle 21
PF1: 28 cycles, needs to be written by cycle 27
PF2: 38.67 cycles, needs to be written by cycle 37
PF0: 49.33 cycles, needs to be written by cycle 48
PF1: 54.67 cycles, needs to be written by cycle 53
PF2: 65.33 cycles, needs to be written by cycle 64

For the right side, reflected:
PF2: starts drawing at cycle 49.33, needs to be written by cycle 48
PF1: 60 cycles, needs to be written by cycle 59
PF0: 70.67 cycles, needs to be written by cycle 69

This may not be correct, but I think it is.

-bob