[stella] PF register write timing

[R Mundschau]

Thomas and Bob,

Thanks for the info.  I have been using cycle 25 for PF1 left.  Those  
2 extra cycles make things a lot easier.

Cheers!
Rob

On May 10, 2006, at 11:48 AM, Thomas Jentzsch wrote:

> Bob Montgomery wrote:
>
>> I've done some testing here and there and I think you basically need
>> at least 1 full machine cycle between the write to the PF register  
>> and
>> when TIA starts drawing that register to the screen.
>
> My rule of thumb is 2/3 CPU cycles before the TIA starts to display.
> This works on almost all machines, but a few (e.g. Gemini and some
> 7800s) seem to have problems with the timing.
>
> This results in some minor differences (*) to Bob's list:
> PF0: 22.67 cycles, needs to be written by cycle 22 *
> PF1: 28.00 cycles, needs to be written by cycle 27
> PF2: 38.67 cycles, needs to be written by cycle 38 *
> PF0: 49.33 cycles, needs to be written by cycle 48
> PF1: 54.67 cycles, needs to be written by cycle 54 *
> PF2: 65.33 cycles, needs to be written by cycle 64
>
> I used these timings in Thrust, so I know pretty well about the
> reliability.
>
> Have fun!
> Thomas
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> Thomas Jentzsch         | *** Every bit is sacred ! ***
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